Smart cards are becoming increasingly more popular for security and personal identification applications. For example, smart cards are currently used for storing sensitive data such as medical records, banking information, etc. In perhaps their most common form, smart cards have a card body which resembles a credit card in size, shape, and thickness, and they may even be made out of similar materials, such as plastic. Yet, rather than simply having a magnetic stripe to store sensitive information (e.g., account numbers, user identification, etc.) as standard credit cards do, smart cards generally include an integrated circuit (IC). The IC not only includes a non-volatile memory for storing such sensitive information, but it may also include a microprocessor for processing this information and communicating with a host device via a card reader, for example. Accordingly, not only can smart cards store more information than magnetic stripe cards, but they also have much greater functionality.
Various protocols have emerged to standardize smart card operation and communications. One of the earliest of these was developed by the International Organization for Standardization (ISO) and is known as the ISO 7816-X protocol. In particular, this protocol is set forth in ISO documents ISO 7816-1 (Physical Characteristics), ISO 7816-2 (Dimensions and Locations of Contacts), ISO 7816-3 (Electronic Signals and Transmission Protocols), ISO 7816-10 (Electronic Signals and Answer to Reset for Synchronous Cards), and ISO 7816-12 (USB Interface), for example, all of which are hereby incorporated herein in their entirety by reference.
Furthermore, in response to the increasing popularity of the universal serial bus (USB) architecture, increasing numbers of smart cards continue to be developed which operate in accordance with the USB protocol. This protocol is set forth in the Universal Serial Bus Specification, Revision 2.0, Apr. 27, 2000, published by USB Implementers Forum, Inc., which is hereby incorporated herein in its entirety by reference. The USB architecture is particularly advantageous in that it provides a standard “plug and play” interface for devices external to a computer, for example. That is, external peripheral devices can be relatively quickly and easily installed and removed from a computer without having to open or power down the computer.
With the ever increasing complexity of applications which are now being implemented using smart cards, these applications correspondingly require significantly higher volumes of data to be transmitted between the smart card and the host device to which it is connected. Accordingly, the ability of a smart card to efficiently buffer this data is important to minimize “bottlenecking” of the data and, thus, underutilization of bus bandwidth and a degradation of system performance.
With respect to the USB environment, there are four types of data transfer modes defined by the USB Specification, namely control mode transfers, bulk mode transfers, interrupt mode transfers, and isochronous mode transfers. While control mode transfers typically involve fairly small amounts of data, the other types of transfers may involve relatively large amounts of data. Moreover, many smart card applications require the use of more than one type of transfer mode, and USB smart cards can run more than one application at a time. Further, the USB Specification defines three data transfer rates that may be used for data transfer, namely low speed (1.5 Mb/s), full speed (12 Mb/s), and high speed (480 Mb/s). As such, the use of the larger volume data transfer modes and higher data transfer rates can significantly complicate the task of data buffering.
Various prior art schemes have been used for buffering data in smart cards, which will now be described with reference to FIGS. 5-11. It should be noted that reference numerals separated by decades in these figures are used to indicate similar elements in the different embodiments (e.g., the buffer 51a is similar to the buffer 61a, etc.). One basic prior art smart card data buffer circuit 50 includes an array of buffers 51a, 51b, and control/gating logic 52 for gating data into and/or out of the storage element array. As illustratively shown, the data buffer circuitry 50 is used for buffering data sent “downstream” from a host device to the smart card via a smart card adapter, for example.
A similar buffer circuit 60 for buffering upstream data (i.e., data sent from the smart card to the host device) is illustratively shown in FIG. 6. The buffers 51a, 51b and 61a, 61b may be implemented with a set of registers, a block of consecutive RAM memory locations, a circular FIFO, or other suitable storage elements, as will be appreciated by those skilled in the art. The pairs of buffers 51a, 51b and 61a, 61b are used in tandem, typically in a “ping-pong” (a.k.a. “toggle buffer”) arrangement so that a continuous flow of serial data is not interrupted, resulting in loss of data.
The buffer circuits 50, 60 are designed so that the buffers 51a, 51b and 61a, 61b are used in coordinated fashion, and so that newly received (or sent) data does not overwrite previously received (or sent) data, until it is safe to do so. The control/gating logic 52, 62 may be implemented with simple Boolean logic in some embodiments or a more complex state machine in other embodiments, as illustrated in FIGS. 5 and 6, and it may be synchronous or asynchronous, as needed.
The above-described unidirectional buffering schemes are generally inadequate for the relatively high volume requirements of USB data transmission due to the bi-directional nature of USB data transfers. Accordingly, another type of data buffer circuit 70 which has been used in some implementations includes bi-directionally accessible buffers 71a, 71b. This configuration allows data to be passed from a USB host to a USB smart card and vice-versa, without using both sets of the buffer elements 51a, 51b and 61a, 61b. This results in cost-savings, and meets the needs of some less data-intensive applications. For example, this configuration often performs satisfactorily for USB low speed control data transfers, where a single data packet payload having a maximum of thirty-two bytes is used.
Even so, a limit will eventually be reached at which the bi-directional toggle buffer circuit 70 becomes inadequate for use in smart card USB Devices. This limit begins to emerge as the transition from control mode to the other three data transfer modes noted above is made to increase the data throughput between the host device and the USB smart card device. This limit is also evident when the data transfer speeds are increased from low speed to full or high speed.
Accordingly, other prior art buffer circuits 80, 90 respectively illustrated in FIGS. 8 and 9 have been used in some implementations as well. With the buffer 80 a dedicated buffer element 81a buffers incoming (i.e., downstream) data, and a pair of buffers 81b, 81c buffer outgoing data, and vice-versa with the buffer circuit 90. In other words, the illustrated configurations are unidirectional tri-buffer schemes. A similar bi-directional tri-buffer scheme is implemented in the buffer circuit 100 illustratively shown in FIG. 10.
Other prior art variations of the above-noted buffer circuits are illustratively shown in FIGS. 11 and 12. In particular, the data buffer circuit 110 implements a unidirectional quad-buffer element scheme, while the buffer circuit 120 implements a bi-directional quad-buffer element scheme. Here again, depending on the nature of the data streaming needed, implementing such buffer configurations may result in a significant increase in circuit complexity and costs. In other words, replicating pairs of buffers increases the cost and complexity of implementation. This is particularly so when two or more OUT endpoints are used to support in excess of 64 bytes of data payload per transaction. As such, data buffering still remains a significant obstacle to achieving high levels of sustainable bandwidth utilization in smart card devices.